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19-2085; Rev 1; 2/03
3-Wire Serial RTC in a TDFN
General Description
The MAX6901 3-wire serial interface real-time clock in a TDFN package contains a real-time clock/calendar and 31 x 8 bits of static RAM (SRAM). The real-time clock/calendar provides seconds, minutes, hours, day, date, month, year, and century information. A time/date-programmable polled ALARM is included in the MAX6901. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. The clock operates in either the 24hr or 12hr format with an AM/PM indicator. A push-pull 32kHz output is also included. The MAX6901 operates with a supply voltage of +2V to +5.5V, is available in the ultra-small 8pin TDFN package, and works over the industrial temperature range, -40C to +85C.
Features
o Real-Time Clock Counts Seconds, Minutes, Hours, Day of Week, Date of Month, Month, Year, and Century o Leap-Year Compensation Valid up to Year 2100 o Wide +2V to +5.5V Operating Voltage Range o 3-Wire Serial Interface, 2MHz at 5V, 500kHz at 2V o 31 x 8-Bit SRAM for Scratchpad Data Storage o Uses Standard 32.768kHz, 12.5pF Watch Crystal o Low Timekeeping Current (400nA at 2V) o Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock Registers or SRAM o 8-Pin 3mm x 3mm x 0.8mm TDFN Surface-Mount Package o Push-Pull 32.768kHz Clock Output o Programmable Time/Date Polled ALARM Function o No External Crystal Bias Resistors or Capacitors Required
MAX6901
Applications
Point-of-Sale Equipment Intelligent Instruments Fax Machines Battery-Powered Products Portable Instruments
Typical Operating Circuit
3.3V 3.3V 2 VCC P1.0 C P1.1 P1.2 CLKIN 1 SCLK MAX6901 7 CS 8 I/O 5 32KHZ GND 6 X1 4 X2 3 32.768kHz CRYSTAL 0.1F
Ordering Information
PART MAX6901ETA-T TEMP RANGE -40C to +85C PINPACKAGE 8 TDFN TOP MARK AGV
Pin Configuration appears at end of data sheet. Functional Diagram appears at end of data sheet.
Related Real-Time Clock Products
PART MAX6900 MAX6901 MAX6902 SERIAL INTERFACE I2CTM compatible 3 wire SPITM compatible ALARM (bits) 31 x 8 31 x 8 31 x 8 ALARM FUNCTION -- Polled Polled OUTPUT FREQUENCY -- 32kHz -- PIN-PACKAGE 6 TDFN 8 TDFN 8 TDFN
I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3-Wire Serial RTC in a TDFN MAX6901
ABSOLUTE MAXIMUM RATINGS
VCC to GND.............................................................-0.3V to +6V All Other Pins to GND ................................-0.3V to (Vcc + 0.3V) Current into Any Pin..........................................................20mA Rate-of-Rise, VCC ............................................................100V/s Continuous Power Dissipation (TA = +70C) 8-Pin TDFN (derate 24.4mW/C above +70C) .........1951.0mW Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection (all pins, Human Body Model) ..................2000V Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER Operating Voltage Range Active Supply Current (Note 2) Timekeeping Supply Current (Note 3) 32kHz OUTPUT Output High Voltage (Note 5) Output Low Voltage (Note 5) Duty Cycle Output Leakage Current VIN = 0 to VCC, 32kHz output disabled VCC = +2.0V VCC = +5.0V VCC = +2.0V VCC = +5.0V VIN = 0 to VCC -10 5 10 VOL VOH VCC = +2.0V, ISINK = 1.5mA VCC = +5.0V, ISINK = 4mA VCC = +2.0V, ISOURCE = -0.4mA VCC = +5.0V, ISOURCE = -1mA 1.8 4.5 0.4 0.4 -10 1.4 2.2 0.6 0.8 10 3-WIRE DIGITAL INPUTS AND OUTPUTS (SCLK, I/O, CS) Input High Voltage Input Low Voltage Input Leakage Current SCLK, RST Capacitance I/O Capacitance I/O Output Low Voltage I/O Output High Voltage VIH VIL V V nA pF pF V V VOH VOL VCC = +2.0V, ISOURCE = -0.4mA VCC = +5.0V, ISOURCE = -1mA VCC = +2.0V, ISINK = 1.5mA VCC = +5.0V, ISINK = 4mA 40 10 1.8 4.5 0.4 0.4 V V % nA SYMBOL VCC ICC ITK VCC = +2.0V VCC = +5V VCC = +2.0V VCC = +5V 0C < TA < +70C 0C < TA < +70C 0.4 1.3 CONDITIONS MIN 2 TYP MAX 5.5 110 800 0.7 1.7 UNITS V A A
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3-Wire Serial RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Figures 4, 5 and Notes 1, 4)
PARAMETER OSCILLATOR X1 to Ground Capacitance (Note 5) X2 to Ground Capacitance (Note 5) 3-WIRE SERIAL TIMING Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall Time CS to CLK Setup CLK to CS Hold CS Inactive Time CS to I/O High Z SCLK to I/O High Z tDC tCDH tCDD tCL tCH fCLK tR, tF tCC tCCH tCWH tCDZ tCCZ VCC = +2V VCC = +5V VCC = +2V VCC = +5V CL = 50pF VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V RL = 1k, CL = 60pF RL = 1k, CL = 60pF VCC = +2V VCC = +5V VCC = +2V VCC = +5V 4 1 240 60 4 1 0 0 0 0 280 70 280 70 VCC = +2V VCC = +5V 1000 250 1000 250 DC DC 0.5 2.0 2000 500 200 50 280 70 800 200 ns ns ns ns ns MHz ns s ns s ns ns 25 25 pF pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6901
Note 1: All parameters are 100% tested at TA = +25C. Limits over temperature are guaranteed by design and not production tested. Note 2: ICC is specified with the I/O grounded, CS high, SCLK = 2MHz at VCC = +5V; SCLK = 500kHz at VCC = +2.0V, 32kHz output enabled, and no load on 32kHz output. Note 3: Timekeeping current is specified with CS = GND, SCLK = GND, I/O = GND, 32kHz = GND, and 32kHz disabled. Note 4: All values referred to VIH min and VIL max levels. Note 5: Guaranteed by design. Not production tested.
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3-Wire Serial RTC in a TDFN MAX6901
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
TIMEKEEPING CURRENT vs. SUPPLY VOLTAGE
MAX6901 toc01
10.0
SUPPLY CURRENT (A)
1.0
0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
Pin Description
PIN 1 2 3 4 5 6 7 8 -- NAME SCLK VCC X2 X1 32KHZ GND CS I/O PAD FUNCTION Serial Clock Input. 3-wire serial clock for I/O data transfers. Power-Supply Pin. Bypass VCC to GND with a 0.1F capacitor. External 32.768kHz Crystal Connection External 32.768kHz Crystal Connection Buffered Push-Pull 32.768kHz Output. When enabled, 32KHZ puts a buffered version of the timekeeping clock. When disabled, 32KHZ is high impedance. The power-on reset (POR) default state of 32KHZ is enabled. Ground Connection Chip-Select Input. Active-high for valid data transfers. Data Input/Output. 3-wire serial data input/output connection. Ground
Detailed Description
The MAX6901 is a real-time clock/calendar with a 3-wire serial interface and 31 8 bits of SRAM. It provides seconds, minutes, hours, day of the week, date of the month, month, and year information, held in seven 8-bit timekeeping registers (Functional Diagram). An on-chip 32.768kHz oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies the parameters for the external crystal, and Figure 1 shows a functional schematic of the oscillator circuit. The MAX6901's register addresses and definitions are described in Tables 2 and 3. Time and calendar data are stored in the registers in binary coded decimal (BCD) format. A polled alarm function is included for scheduled timing of user-defined times or intervals.
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Command and Control
Address/Command Byte
Each data transfer into or out of the MAX6901 is initiated by an Address/Command byte. The Address/ Command byte specifies which registers are to be accessed, and if the access is a read or a write. Table 2 shows the Address/Command bytes and their associated registers, and Table 3 lists the hex codes for all read and write operations. The Address/Command bytes are input LSB (bit 0) first. Bit 0 specifies a write (logic 0) or read (logic 1). Bits 1 to 5 specify the designated register to be written or read. Bit 6 specifies register data (logic 0), or RAM data (logic 1). The MSB (bit 7) must be logic 1. If the MSB is a zero, writes to the MAX6901 are disabled.
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3-Wire Serial RTC in a TDFN MAX6901
Table 1. Acceptable Quartz Crystal Parameters
PARAMETER Frequency Equivalent Series Resistance (ESR) Parallel Load Capacitance Q Factor SYMBOL f Rs CL Q 40 11.2 40,000 12.5 MIN TYP 32.76 60 13.7 60,000 MAX UNITS kHz k pF
data bits are output until all 31 bytes have been read, or until CS is driven low.
Rf MAX6901
Setting the Clock
Writing to the Timekeeping Registers
Rd
Cg 25pF
Cd 25pF
X1
X2 EXTERNAL CRYSTAL
Figure 1. Oscillator Circuit Schematic
Clock Burst Mode
Accessing the Clock Burst register specifies burstmode operation. In this mode, multiple bytes are read or written with a single Address/Command write. If the Clock Burst register is accessed (BEh for Write and BFh for Read), the first seven clock/calendar registers (Seconds, Minutes, Hours, Date, Month, Day, and Year) and the Control register, are consecutively read or written, starting with the LSB of the Seconds register. When writing to the clock registers in burst mode, all seven registers must be written in order for the data to be transferred (see Example: Setting the Clock with a Burst Write).
The Time and Date are set by writing to the timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year, and Century). During a write operation, an input buffer accepts the new time data while the timekeeping registers continue to increment normally, based on the crystal counter. The buffer also keeps the timekeeping registers from changing as the result of an incomplete Write operation, and collision detection circuitry ensures that a time write does not occur coincident with a Seconds register increment. The updated time data are loaded into the timekeeping registers on the falling edge of CS, at the end of the 3-wire serial Write operation. An incomplete Write operation aborts the update procedure, and the contents of the input buffer are discarded. The timekeeping registers reflect the new time, beginning with the first Seconds register increment after the falling edge of CS. Although both Single Writes and Burst Writes are possible, the best way to write to the timekeeping registers is with a Burst Write. With a Burst Write, main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year), and the Control register are written sequentially following the Address/Command byte. They must be written as a group of eight registers, with 8 bits each, for proper execution of the Burst Write function. All seven timekeeping registers are simultaneously loaded into the clock counters by the falling edge of CS, at the end of the 3-wire serial Write operation. For a normal burst data transfer, the worst-case error that can occur between the actual time and the written time update is 1 second. If Single Write operations are used to enter data into the timekeeping registers, error checking is required. If the Seconds register is not to be written, then begin by reading the Seconds register and save it as initial-seconds. Write to the required timekeeping registers and
RAM Burst Mode
Sending the RAM Burst Address/Command specifies Burst-Mode operation. In this mode, the 31 RAM registers can be consecutively read or written, starting with bit 0 of address C0h for Writes, and C1h for Reads. Burst Read outputs all 31 registers of RAM. When writing to RAM in burst mode, it is not necessary to write all 31 bytes for the data to transfer; each complete byte written is transferred to RAM. When reading from RAM,
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3-Wire Serial RTC in a TDFN MAX6901
Table 2. Register Address/Definition
REGISTER ADDRESS FUNCTION TIMEKEEPING SECOND RD /W 00-59 *POR STATE 00-59 *POR STATE 00-23 01-12 *POR STATE 01-28/29 01-30 01-31 *POR STATE RD /W 01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE 0 WP *POR STATE 00-99 *POR STATE 0 0 32kHz EN 0 ALM OUT 0 12/24 0 1/0 0 0 0 0 10 SEC 0 0 0 1 SEC 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
MINUTE
1
0
0
0
0
0
1
RD /W
10 MIN 0 0 0
1 MIN 0 0 0
HOUR
1
0
0
0
0
1
0
RD /W
10 HR 10 A/P HR 0/1 0 0 0
1 HR
0
0
0
DATE
1
0
0
0
0
1
1
RD /W
0 0 0 0 0 0
0 10 DATE 0 0 0 0 0 0 0 0
1 DATE 0 0 1
MONTH
0 10M 0 0 0 0 0 0 0 0 0
1 MONTH 0 0 1
1
0
0
0
1
0
0
DAY
1
0
0
0
1
0
1
RD /W
WEEKDAY 0 0 1
YEAR
1
0
0
0
1
1
0
RD /W
10 YEAR 1 0 0 1 0 0 1 0 0 0 0 0
1 YEAR 0 0 0 0 0 0 0 0 0
CONTROL
1
0
0
0
1
1
1
RD /W
CENTURY
1
0
0
1
0
0
1
RD /W
1000 YEAR 0 0 1 1
100 YEAR 0 0 1
Note: *POR STATE defines power-on reset state of register content.
then read the Seconds register again (final-seconds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. If the Seconds register is to be written, update the Seconds register
first, and then read it back and store its value (initialseconds). Update the remaining timekeeping registers and then read the Seconds register again (final-sec-
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3-Wire Serial RTC in a TDFN MAX6901
Table 2. Register Address/Definition (continued)
REGISTER ADDRESS FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 MONTH D3 D2 D1 MINUTE 0 1 1 1 1 1 1 1 1 1 D0 SECOND 0 1 1 1 1 1 1 1 1 1
ALARM CONFIG
1
0
0
1
0
1
0
RD /W *POR STATE
0
0 0
0 0 0
0 0 0
0 0 0
0 0 0
RESERVED Do not write to this location. ALARM THRESHOLDS SECOND 1 0 0 1 1 0 0 1 0 0 1 0 1 1
RD /W
*POR STATE
0
RD /W
00-59 *POR STATE 00-59 *POR STATE 00-23 01-12 *POR STATE 01-28/29 01-30 01-31 *POR STATE
0 0 0 0 12/24 0 1/0 1 0 1 1
10 SEC 1 1 1
MINUTE
1
0
0
1
1
0
1
RD /W
10 MIN 1 1 1
HOUR
1
0
0
1
1
1
0
RD /W
10 HR 10 A/P HR 0/1 1 1 1
DATE
1
0
0
1
1
1
1
RD /W
0 0 0 0 0 0
0 10 DATE 0 0 0 0 0 1 1 1
1 DATE 1
MONTH
1
0
1
0
0
0
0
RD /W
01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE
0 10 M 0 0 0 1 0 0 1 0 0
1 MONTH 1
DAY
1
0
1
0
0
0
1
RD /W
1
YEAR
1
0
1
0
0
1
0
RD /W
10 YEAR 1 1 1 1 1
1 YEAR 1
CLOCK BURST
1
0
1
1
1
1
1
RD /W
Note: *POR STATE defines power-on reset state of register content.
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HOUR 0 1 1 1 1 1
YEAR
DATE
DAY
1 SEC
1 MIN
1 HR
WEEKDAY
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3-Wire Serial RTC in a TDFN MAX6901
Table 2. Register Address/Definition (continued)
REGISTER ADDRESS FUNCTION RAM RAM 0 * * * RAM 30 1 1 1 1 1 0 0 * * * 1 1 1 0 RD /W 0 0 0 RD /W RAM DATA 0 * * * RAM DATA 30 x x x x x x x * * * x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 D3 D2 D1 D0
RAM BURST
1
1
1
1
1
1
1
RD /W
Note: *POR STATE defines power-on reset state of register content.
onds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. Note: After writing to any time or date register, no read or write operations are allowed for 45s.
AM/PM and 12Hr/24Hr Mode
Bit 7 of the Hours register selects 12hr or 24hr mode. When high, 12hr mode is selected. In 12hr mode, bit 5 is the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is the second 10hr bit, logic high for hours 20 through 23.
Write-Protect Bit
Bit 7 of the Control register is the write-protect bit. When high, the write-protect bit prevents write operations to all registers except itself. After initial settings are written to the timekeeping registers, set the writeprotect bit to logic 1 to prevent erroneous data from entering the registers during power glitches or interrupted serial transfers. The lower 7 bits (bits 0-6) are unusable, and always read zero. Any data written to bits 0-6 are ignored. Bit 7 must be set to zero before a single byte write to the clock, before a write to RAM, or during a burst write to the clock.
11h, B0h, 04h, 07h, 04h, 02h, and 00h (Table 2). BEh accesses the Clock Burst Write register. The first byte, B1h, sets the Seconds register to 31, and disables the 32.768kHz output. The second byte, 11h, sets the Minutes register to 11. The third byte, B0h, sets the Hours register to 12hr mode, and 10PM. The fourth byte, 04h, sets the Date register (day of the month) to the 4th. The fifth byte, 07h, sets the Month register to July. The sixth byte, 04h, sets the Day register (day of the week) to Thursday. The seventh byte, 02h, sets the Year register to 02. The eighth byte, 00h, clears the write-protect bit of the Control register to allow writing to the MAX6901. The Century register is not accessed with a Burst Write and therefore must be written to separately to set the century to 20. Note the Century register corresponds to the thousand and hundred digits of the current year and defaults to 19.
Reading the Clock
Reading the Timekeeping Registers
The main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) can be read with either Single Reads or a Burst Read. In the MAX6901, a latch buffers each clock counter's data. Clock counter data are latched by the 3-wire serial Read command (on the falling edge of SCLK, after the Address/Command byte has been sent by the Master to read a timekeeping register). Collision-detection circuitry ensures that this
Example: Setting the Clock with a Burst Write
To set the clock with a Burst Write operation to 10:11:31PM, Thursday July 4th, 2002, write BEh as Address/Command byte, followed by 8 bytes, B1h,
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3-Wire Serial RTC in a TDFN MAX6901
Table 3. HEX Register Address/Description
WRITE ADDRESS/COMMAND BYTE (HEX) 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 BE C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 D6 D8 DA DC DE E0 E2 READ ADDRESS/COMMAND BYTE (HEX) 81 83 85 87 89 8B 8D 8F 91 93 95 97 99 9B 9D 9F A1 A3 A5 BF C1 C3 C5 C7 C9 CB CD CF D1 D3 D5 D7 D9 DB DD DF E1 E3 DESCRIPTION SECONDS MINUTES HOUR DATE MONTH DAY YEAR CONTROL RESERVED CENTURY ALARM CONFIGURATION RESERVED SECONDS ALARM THRESHOLD MINUTES ALARM THRESHOLD HOURS ALARM THRESHOLD DATE ALARM THRESHOLD MONTH ALARM THRESHOLD DAY ALARM THRESHOLD YEAR ALARM THRESHOLD CLOCK BURST RAM 0 RAM 1 RAM 2 RAM 3 RAM 4 RAM 5 RAM 6 RAM 7 RAM 8 RAM 9 RAM 10 RAM 11 RAM 12 RAM 13 RAM 14 RAM 15 RAM 16 RAM 17 POR CONTENTS (HEX) 00 00 00 01 01 01 70 00 Nonapplicable 19 00 07 7F 7F BF 3F 1F 07 FF Nonapplicable Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
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3-Wire Serial RTC in a TDFN MAX6901
Table 3. HEX Register Address/Description (continued)
WRITE ADDRESS/COMMAND BYTE (HEX) E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE READ ADDRESS/COMMAND BYTE (HEX) E5 E7 E9 EB ED EF F1 F3 F5 F7 F9 FB FD FF DESCRIPTION RAM 18 RAM 19 RAM 20 RAM 21 RAM 22 RAM 23 RAM 24 RAM 25 RAM 26 RAM 27 RAM 28 RAM 29 RAM 30 RAM Burst POR CONTENTS (HEX) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Nonapplicable
does not happen coincident with a Seconds counter increment to ensure accurate time data is being read. The clock counters continue to count and keep accurate time during the Read operation. The simplest way to read the timekeeping registers is to use a Burst Read. In a Burst Read, the main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) and the Control register are read sequentially in the order listed with the Seconds register first. They are read out as a group of eight registers, with 8 bits each. All timekeeping registers (except Century) are latched upon the receipt of the Burst Read command. The worst-case error between the "actual" time and the "read" time is 1 second for a normal data transfer. The timekeeping registers may also be read using Single Reads. If Single Reads are used, it is necessary to do some error checking on the receiving end, because it is possible that the clock counters could change during the Read operations, and report inaccurate time data. The potential for error is when the Seconds register increments before all the registers are read. For example, suppose a carry of 13:59:59 to 14:00:00 occurs during Single Read operations. The net data read could be 14:59:59, which is erroneous. To prevent errors from occurring with Single Read operations, read the Seconds register first (initial-seconds) and store this value for future comparison. After the remaining timekeeping registers have been read, reread the Seconds register (final-seconds). Check that
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the final-seconds value equals the initial-seconds value; if not, repeat the entire Single Read process. Using Single Reads at a 100kHz serial speed, it takes under 2.5ms to read all seven of the timekeeping registers, including two reads of the Seconds register.
Example: Reading the Clock with a Burst Read
To read the time with a Burst Read, send BFh as the Address/Command byte. Then clock out 8 bytes, Seconds, Minutes, Hours, Date of the month, Month, Day of the week, Year, and finally the Control byte. All data are output LSB first. Decode the required information based on the register definitions listed in Table 2.
Using the Alarm
A polled alarm function is available by reading the ALM OUT bit. The ALM OUT bit is D7 of the Minutes timekeeping register. A logic 1 in ALM OUT indicates the alarm function is triggered. There are eight registers associated with the alarm function, seven programmable Alarm Threshold registers and one programmable Alarm Configuration register. The Alarm Configuration register determines which Alarm Threshold registers are compared to the timekeeping registers, and the ALM OUT bit sets if the compared registers are equal. Table 2 shows the function of each bit of the Alarm Configuration register. Placing a logic 1 in any given bit of the Alarm Configuration register enables the respec-
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3-Wire Serial RTC in a TDFN
tive alarm function. For example, if the Alarm Configuration register is set to 0000 0011, ALM OUT is set when both the minutes and seconds indicated in the Alarm Threshold registers match the respective timekeeping registers. Once set, ALM OUT stays high until it is cleared by reading or writing to the Alarm Configuration register, or by reading or writing to any of the Alarm Threshold registers. The Alarm Configuration register is written with Address/Command 94h, and read with Address/Command 95h. by driving CS high. If CS is low, I/O is high impedance. At power-up, CS must be low until VCC 2.0V.
MAX6901
Serial Clock
A clock cycle on SCLK is a rising edge followed by a falling edge. For data input, data must be valid at I/O during the rising edge of the clock. For data outputs, bits are valid on I/O after the falling edge of clock. Also, SCLK must be low when CS is driven high.
Data Input (Single-Byte Write)
Following the eight SCLK cycles that input a SingleByte Write Address/Command, data bits are input on the rising edges of the next eight SCLK cycles. Additional SCLK cycles are ignored. Input data LSB first.
Using the On-Board RAM
The static RAM is 31 x 8 bits addressed consecutively in the RAM address space. Even-addressed commands (C0h-FCh) are used for Writes, and oddaddressed commands (C1h-FDh) are used for Reads. The contents of the RAM are static and remain valid for V CC down to 2V. All RAM data are lost if power is cycled. The write-protect bit (bit 7 of the Control register), when high, disallows any changes to RAM.
Data Input (Burst Write)
Following the eight SCLK cycles that input a Burst Write Address/Command, data bits are input on the rising edges of the following SCLK cycles. The number of clock cycles depends on whether the timekeeping registers or RAM are being written. A clock Burst Write requires an Address/Command byte, 7 timekeeping data bytes, and 1 Control register byte. A Burst Write to RAM may be terminated after any complete data byte by driving CS low. Input data LSB first (Figures 3 and 5).
3-Wire Serial Interface
Interfacing the MAX6901 with a microcontroller is accomplished by using a 3-wire, synchronous, serial interface. Required to communicate are a Chip Select signal (CS), a Serial Clock signal (SCLK), and a Data line (I/O). All data transfers are framed by the CS signal that must be active-high for any data transfer to occur. At the beginning of any data transfer (rising edge of CS), SCLK should be low. This prevents the MAX6901 from misinterpreting the transition of CS as a high-to-low transition of SCLK (if SCLK were to be left high when CS transitions from a low to high). The first 8 bits sent after CS is pulled high by the microcontroller comprise the Address/Command Byte, which tells the MAX6901 if the data transfer is a read or a write, and which register is read to or written from. Data are clocked into the MAX6901, through the I/O pin, on the rising edges of SCLK, and data are clocked out on the falling edge of SCLK. Data format is always LSB first to MSB last. When CS is low, I/O is high impedance. Single data transfer timing is shown in Figure 2. Burstmode data transfer timing is shown in Figure 3. Detailed Read and Write timing diagrams are shown in Figures 4 and 5, respectively.
Data Output (Single-Byte Read and Burst Read)
A read from the MAX6901 is initiated by an Address/ Command Write from the microcontroller (master) to the MAX6901 (slave). The Address/Command Write portion of the data transfer is clocked into the MAX6901 on rising clock edges. On the eighth rising SCLK edge, the last bit of the Address/Command Byte is clocked into the MAX6901. After t CDH (CLK to Data Hold time, Figure 4), the microcontroller must release the data line. On the eighth falling edge of SCLK, the MAX6901 takes control of the data line and begins to output data. The MAX6901 outputs data on the falling edge of SCLK after tCDD (CLK to Data Delay time, Figure 4). On the next rising edge of SCLK, I/O goes to high impedance after tCCZ (which is specified with a maximum time). Minimum time for tCCZ can be 0ns. Since the I/O line can go to high impedance on the rising edge of SCLK, it is best to read the data from the MAX6901 before the rising edge of SCLK but after tCDD (CLK to Data Delay time). This is best accomplished through the microcontroller I/O port pins by writing a low to SCLK, waiting tCDD (CLK to Data Delay time), reading the MAX6901 I/O pin, and then writing a high to SCLK. Data bytes are output LSB first. Additional SCLK cycles transmit additional data bits, as long as CS remains high. This permits continuous burst-mode read capability.
11
Chip Select
CS serves two functions. First, CS turns on the control logic that allows access to the Shift register for Address/Command and data transfer. Second, CS provides a method of terminating either single-byte or multiple-byte data transfers. All data transfers are initiated
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN MAX6901
(a) 3-WIRE SINGLE BYTE READ:
CS
SCLK
A0 I/O 1
A1 A1
A2 A2
A3 A3
A4 A4
A5 A5
A6 R
A7 1
D0
D1
D2
D3
D4
D5
D6
D7
ADDRESS/COMMAND BYTE R = RAM/ REGISTER SELECT BIT RAM = 1, REGISTER = 0
I/O DATA BYTE
(b) 3-WIRE SINGLE BYTE WRITE:
CS
SCLK
A1 I/O 0 A1
A2 A2
A3 A3
A4 A4
A5 A5
A6 R
A7 1
D0
D1
D2
D3
D4
D5
D6
D7
ADDRESS/COMMAND BYTE R = RAM/ REGISTER SELECT BIT RAM = 1, REGISTER = 0
I/O DATA BYTE
Figure 2. Single Byte Data Transfer
32.768kHz Output (32KHZ)
32KHZ is a push-pull 32.768kHz output for timing or clocking of external devices. Bit D7 in the Clock Seconds register is the active-low enable bit for 32KHZ. When D7 is logic 0, 32KHZ is enabled. When logic 1, 32KHZ is disabled and set to high impedance. Poweron reset enables the 32.768kHz output.
Table 4. In addition to the specified SMT devices, some of the listed manufacturers also offer other package options.
Frequency Stability and Temperature
Timekeeping accuracy of the MAX6901 is dependent on the frequency stability of the external crystal. To determine frequency stability, use the parabolic curve in Figure 6 and the following equations: f = fk (T0 - T)2 where: f = change in frequency from +25C
Applications Information
Crystal Selection
The MAX6901 is designed to use a standard 32.768kHz watch crystal. Table 1 details the recommended crystal requirements. Some suggested crystals are listed in
12
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN
()
MAX6901
CS
SCLK
A0 I/O 1
A1 1
A2 1
A3 1
A4 1
A5 1
A6 R
A7 1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
ADDRESS/COMMAND BYTE R = RAM/ REGISTER SELECT BIT RAM = 1, REGISTER = 0
I/O DATA BYTE 1
I/O DATA BYTE N N = 8 FOR TIMEKEEPING REGISTER BURST N = 31 MAX FOR RAM BURST
(b) 3-WIRE BURST WRITE:
CS
SCLK
A0 I/O 0
A1 1
A2 1
A3 1
A4 1
A5 1
A6 A7 R 1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
ADDRESS/COMMAND BYTE R = RAM/ REGISTER SELECT BIT RAM = 1, REGISTER = 0
I/O DATA BYTE 1
I/O DATA BYTE N N = 8 FOR TIMEKEEPING REGISTER BURST N = 31 MAX FOR RAM BURST
Figure 3. Burst Mode Data Transfer
f = nominal crystal frequency k = parabolic curvature constant (-0.035ppm/C2 0.005ppm/C2 for 32.768kHz watch crystals) T0 = turnover temperature (+25C 5C for 32.768kHz watch crystals) T = temperature of interest (C) For example: What is the worst-case change in oscillator frequency from +25C ambient to +45C ambient? fdrift = 32,768 (-0.04 (1 10-6)) (20-45)2 = -0.8192Hz What is the worst-case timekeeping error per second?
Error due to temperature drift: tdrift = {[1 / [(f+fdrift) / 32768]]-1s} / 1s tdrift = {[1 / [(32768 - 0.8192) / 32768]]-1}/1s = 0.000025s/s Error due to +25C initial crystal tolerance of 20ppm: finitial = 32,768 (-20 ((1 10-6)) = -0.65536Hz tinitial = {[1 / [(f+finitial) / 32768]]-1s} / 1s tinitial = {[1 / [(32768-0.65536) / 32768]]-1} / 1s = 0.000025s/s Total timekeeping error per second:
13
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN MAX6901
CS tCC SCLK tCCZ tCDD tCDD 0 1 7 0 1 tCDZ
tCDH I/O tDC
READ ADDRESS/COMMAND BYTE
READ DATA BIT
Figure 4. 3-Wire Read Data Transfer Serial Timing Diagram
tCWH CS tCC tCL tCCH tF
tR
SCLK tCDH tDC tCDH
I/O
0
1
7
0
WRITE ADDRESS/COMMAND BYTE
WRITE DATA BIT
Figure 5. 3-Wire Write Data Transfer Serial Timing Diagram
ttotal = tdrift + tinitial ttotal = 0.00002+0.000025=0.000045s/s After 1 month, that translates to: hr min s t = (31 days) x 24 x 60 x x 60 day hr min
Oscillator Start Time
The MAX6901 oscillator typically takes 5s to 10s to begin oscillating. To ensure the oscillator is operating correctly, the software should validate proper timekeeping. This is accomplished by reading the Seconds register. Any reading of 1s or more from the POR value of zero is a validation of proper startup.
(0.00045s / s) = 120.528s
Total worst-case timekeeping error at the end of 1 month at +45C is about 120s or 2 min (assumes negligible parasitic layout capacitance).
Power-On Reset
The MAX6901 contains an integral POR circuit that ensures all registers are reset to a known state on power-up. Once VCC rises above 1.6V (typ), the POR circuit releases the registers for normal operation. When
14
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN MAX6901
Table 4. 32.768kHz Surface-Mount Watch Crystals
MANUFACTURER Abracon Corporation Caliber Electronics ECS INC International Fox Electronics M-tron Raltron SaRonix MANUFACTURER PART NO. ABS25-32.768-12.5-B-2-T AWS2A-32.768kHz, ECS-.327-12.5-17 FSM327 SX2010/ SX2020 RSE-32.768-12.5-C-T 32S12A TEMP. RANGE -40C to +85C -20C to +70C -10C to +60C -40C to +85C -20C to +75C -10C to +60C -40C to +85C CL (pF) 12.5 12.5 12.5 12.5 12.5 12.5 12.5 +25C FREQUENCY TOLERANCE (ppm) 20 20 20 20 20 20 20
TEMPERATURE (C)
-50 -40 -30 -20 -10 0 0 10 20 25 30 40 50 60 70 80 90
-50
f (ppm)
-100
-150
if the I/O is allowed to float. If minimum timekeeping current is desired, the microcontroller port pin should be configured as an input with a weak pullup. Alternatively, use a 100k or less pulldown or pullup resistor (for microcontroller port pins with 1A input leakage). There are similar considerations for 32KHZ if it is placed in its high-impedance state. For lowest timekeeping current, it should not be allowed to float. Force it high or low, or terminate it with a pullup or pulldown resistor.
-200
-250 TYPICAL TEMPERATURE CHARACTERISITICS (k = 0.035ppm/C2, TO = +25C)
Timekeeping Current--Battery Backup Systems
Often times, an RTC is operated in a system with a backup battery. A microprocessor supervisory circuit with backup battery switchover, or other switching arrangement, is used to switch power from V CC to VBATT when VCC falls below a set threshold. Most of these systems leave only the RTC and some SRAM to run from VBATT. The microcontroller that communicates with the RTC is powered only from V CC . When the microcontroller is reset, its port pins typically become high impedance. This essentially floats I/O, CS, and SCLK on the MAX6901. There is a potential for increased timekeeping current (up to x100) as VCC falls through the linear region of the input gates for I/O, SCLK, and CS. The duration of this effect depends on the discharge rate of VCC. To minimize current draw from V BATT in such systems, ensure that V CC falls rapidly at power down. One option is a VCC discharge resistor of 100k or less from VCC to ground. This also ensures sufficient impedance when VCC is gone back through the microcontroller's ESD protection, to keep I/O, SCLK, and CS from floating. Alternately, a 100k pulldown (for microcontroller port pins with 1A input leakage) on each pin (I/O, SCLK, and CS) ensures that timekeeping current specifications are met during the power switchover.
15
Figure 6. Typical Temperature Curve for 32.768kHz Watch Crystal
VCC drops to less than 1.6V (typ), the MAX6901 resets all register contents to the POR defaults (Table 2).
RESERVED Registers
Addresses/Commands 90h, 91h, 96h, and 97h are reserved for factory testing ONLY. Do not write to these registers. If inadvertent Writes are done to any of these registers, cycle power to the MAX6901.
Power-Supply Considerations
For most applications, a 0.1F capacitor from VCC to GND provides adequate bypassing for the MAX6901. A series resistor can be added to the supply line for operation in extremely harsh or noisy environments.
Timekeeping Current--Normal Operation
When I/O is high impedance (CS = low, or after each rising-clock edge for a data output transfer), there is a potential for increased timekeeping current (up to 100x)
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN MAX6901
GROUND PLANE VIA CONNECTION
GUARD RING
VCC PLANE VIA CONNECTION
*
0.1F SM CAP
*
* *
GROUND PLANE VIA CONNECTION
**
* *
MAX6901
*
* *
SM WATCH CRYSTAL
** *
*
**
*LAYER 1 TRACE GROUND PLANE VIA CONNECTION ** LAYER 2 LOCAL GROUND PLANE CONNECT ONLY TO PIN 6 GROUND PLANE VIA
Figure 7. Printed Circuit Board Layout for Crystal Connections
There are similar considerations for 32KHZ if it is placed in its high-impedance state. For lowest timekeeping current, it should not be allowed to float. Force it high or low, or terminate it with a pullup or pulldown resistor.
ground plane, and tied to ground at the MAX6901 ground pin. Restrict the plane to be no larger than the perimeter of the guard ring. Do not allow this ground plane to contribute significant capacitance between X1 and X2.
PC Board Layout Considerations
The MAX6901 uses a very-low-current oscillator to minimize supply current. This causes the oscillator pins, X1 and X2, to be relatively high impedance. Exercise care to prevent unwanted noise pickup. Connect the 32.768kHz crystal directly across X1 and X2 of the MAX6901. To eliminate unwanted noise pickup, design the PC board using these guidelines (Figure 7): place the crystal as close to X1 and X2 as possible and keep the trace lengths short; place a guard ring around the crystal, X1 and X2 traces (where applicable), and connect the guard ring to GND; keep all signal traces away from beneath the crystal, X1, and X2. Finally, an additional local ground plane can be added under the crystal on an adjacent PC board layer. The plane should be isolated from the regular PC board
16
Chip Information
TRANSISTOR COUNT: 26,214 PROCESS: CMOS
______________________________________________________________________________________
3-Wire Serial RTC in a TDFN
Functional Diagram
X1 X2 1Hz OSCILLATOR 32.768kHz DIVIDER SECONDS MINUTES HOURS 32kHz DATE CS CONTROL LOGIC MONTH DAY SCLK I/O INPUT SHIFT REGISTERS ADDRESS REGISTER YEAR CONTROL CENTURY ALARM CONFIGURATION 31 x 8 RAM TEST CONFIGURATION ALARM THRESHOLDS VCC GND CLOCK BURST RAM BURST ALARM OUT
MAX6901
ALARM CONTROL LOGIC
Pin Configuration
TOP VIEW
SCLK 1 VCC 2
8 I/O 7 CS
MAX6901
X2 3 6 GND 5 32KHZ X1 4
TDFN
______________________________________________________________________________________
17
3-Wire Serial RTC in a TDFN MAX6901
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, QFN THIN.EPS
1 2
L D A A2
PIN 1 ID
D2
1
N
1
b
PIN 1 INDEX AREA
C0.35 [(N/2)-1] x e REF. e
E
DETAIL A
E2
A1
k
C L
C L
L e A e
L
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0137
D
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.50-0.10 1.50-0.10 1.50-0.10 E2 2.30-0.10 2.30-0.10 2.30-0.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.40-0.05 0.30-0.05 0.25-0.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL DOCUMENT CONTROL NO. REV.
2 2
21-0137
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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